VHDL在电路设计中的应用

English | PDF | 1991 | 249 Pages | ISBN : 1461367700 | 50.82 MB

VHDL is an industry standardmodeling language for the designanddescription of elec- tronic systems. Although intended for digital hardware design, VHDL contains features found in modem programming, hardware description, and C.A.E. design and simulation languages. Thisricll feature set is allowing the language La be adopted by a largerand more diversified audience than for any other hardware design I description language (HDL). It is for this audience of users that this book is wriuen.

VHDL 是一种用于电子系统设计和描述的行业标准建模语言。尽管旨在针对数字硬件设计，VHDL 包含了许多现代编程、硬件描述以及 CAE 设计与仿真的语言中所发现的功能特性。这一丰富的功能集使该语言能够被更大的且更加多元化的用户群体所采用，比其他任何一种硬件设计描述语言（HDL）的采用者都要多。这本书就是为这个用户群体而写的。

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